From b4e56f960ecb647e64e6330b8d4a8a335161883b Mon Sep 17 00:00:00 2001
From: "zaccaria.majid" <zaccaria.majid@egalware.com>
Date: Thu, 27 Jul 2023 17:07:27 +0200
Subject: [PATCH] fix gestione cartelle per file processati

---
 SMGen/Pages/SMEvent2State.razor               |  6 +-
 SMGen/Pages/SMEvent2State.razor.cs            | 13 ++-
 SMGen/Pages/SMIn2Event.razor.cs               |  7 +-
 .../PROCESSED/{ => BIT}/10049_LVF_FANUC.csv   |  0
 .../{ => BIT}/10063_SEGHETTO_DANOBAT.csv      |  0
 .../{ => BIT}/10066_FLUITEK_SEMAPHORE.csv     |  0
 .../{ => BIT}/10067_FLUITEK_FEMCO.csv         |  0
 .../{ => BIT}/10_Mitsubishi_simple.csv        |  0
 SMGen/Temp/Rules/PROCESSED/{ => BIT}/11.csv   |  0
 SMGen/Temp/Rules/PROCESSED/{ => BIT}/15.csv   |  0
 SMGen/Temp/Rules/PROCESSED/{ => BIT}/17.csv   |  0
 SMGen/Temp/Rules/PROCESSED/{ => BIT}/18.csv   |  0
 SMGen/Temp/Rules/PROCESSED/{ => BIT}/19.csv   |  0
 .../PROCESSED/{ => BIT}/1_Simple_Machine.csv  |  0
 .../Rules/PROCESSED/{ => BIT}/20_nikkei.csv   |  0
 .../Rules/PROCESSED/{ => BIT}/21_DMG1035.csv  |  0
 .../Rules/PROCESSED/{ => BIT}/22_COSMAP.csv   |  0
 .../PROCESSED/{ => BIT}/23_EMCO_LM600.csv     |  0
 .../PROCESSED/{ => BIT}/24_EMCO_MM500.csv     |  0
 .../{ => BIT}/25_ABB_BTB_TECNOTRANSFER.csv    |  0
 .../{ => BIT}/26_ABB_DOOSAN_main.csv          |  0
 .../{ => BIT}/27_ABB_DOOSAN_pallet.csv        |  0
 .../PROCESSED/{ => BIT}/28_ABB_RIELLO.csv     |  0
 .../PROCESSED/{ => BIT}/29_EMCO_LM1200.csv    |  0
 .../Rules/PROCESSED/{ => BIT}/2_Caber.csv     |  0
 .../PROCESSED/{ => BIT}/30_SCATOLE_INTEC.csv  |  0
 .../Rules/PROCESSED/{ => BIT}/46_OSAI_CMS.csv |  0
 .../PROCESSED/{ => BIT}/54_STD_base_6bit.csv  |  0
 .../PROCESSED/{ => BIT}/5_MoriSeiki_main.csv  |  0
 .../PROCESSED/{ => BIT}/60_STD_MACHINE.csv    |  0
 .../PROCESSED/{ => BIT}/61_STD_DP_MAIN.csv    |  0
 .../PROCESSED/{ => BIT}/62_STD_DP_TAV.csv     |  0
 .../{ => BIT}/66_FLUITEK_SEMAPHORE.csv        |  0
 .../PROCESSED/{ => BIT}/67_FLUITEK_FEMCO.csv  |  0
 .../{ => BIT}/6_MoriSeiki_pallet.csv          |  0
 .../{ => BIT}/7_MoriSeiki_simple.csv          |  0
 .../Rules/PROCESSED/{ => BIT}/8_TAV_1_IMP.csv |  0
 .../Rules/PROCESSED/{ => BIT}/9_TAV_2_IMP.csv |  0
 .../{ => STATI}/12_FAMIGLIA_JETCO.csv         | 88 +++++++++++++++++++
 .../12_FAMIGLIA_JETCO_CONFRONTO.csv           |  0
 .../{ => STATI}/1_BARCODE_MANUALE.csv         |  0
 .../1_BARCODE_MANUALE_CONFRONTO.csv           |  0
 SMGen/appsettings.json                        |  2 +
 43 files changed, 111 insertions(+), 5 deletions(-)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/10049_LVF_FANUC.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/10063_SEGHETTO_DANOBAT.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/10066_FLUITEK_SEMAPHORE.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/10067_FLUITEK_FEMCO.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/10_Mitsubishi_simple.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/11.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/15.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/17.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/18.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/19.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/1_Simple_Machine.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/20_nikkei.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/21_DMG1035.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/22_COSMAP.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/23_EMCO_LM600.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/24_EMCO_MM500.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/25_ABB_BTB_TECNOTRANSFER.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/26_ABB_DOOSAN_main.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/27_ABB_DOOSAN_pallet.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/28_ABB_RIELLO.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/29_EMCO_LM1200.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/2_Caber.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/30_SCATOLE_INTEC.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/46_OSAI_CMS.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/54_STD_base_6bit.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/5_MoriSeiki_main.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/60_STD_MACHINE.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/61_STD_DP_MAIN.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/62_STD_DP_TAV.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/66_FLUITEK_SEMAPHORE.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/67_FLUITEK_FEMCO.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/6_MoriSeiki_pallet.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/7_MoriSeiki_simple.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/8_TAV_1_IMP.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => BIT}/9_TAV_2_IMP.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => STATI}/12_FAMIGLIA_JETCO.csv (67%)
 rename SMGen/Temp/Rules/PROCESSED/{ => STATI}/12_FAMIGLIA_JETCO_CONFRONTO.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => STATI}/1_BARCODE_MANUALE.csv (100%)
 rename SMGen/Temp/Rules/PROCESSED/{ => STATI}/1_BARCODE_MANUALE_CONFRONTO.csv (100%)

diff --git a/SMGen/Pages/SMEvent2State.razor b/SMGen/Pages/SMEvent2State.razor
index bddb4dc..53773c1 100644
--- a/SMGen/Pages/SMEvent2State.razor
+++ b/SMGen/Pages/SMEvent2State.razor
@@ -25,4 +25,8 @@
             <button @onclick="()=>Read_rule_file_transitions()">Process</button>
         }
     </div>
-</div>
\ No newline at end of file
+</div>
+
+<FilesList PagerResetReq="pgResetReq" updateRecordCount="UpdateTotCount" currFilter="@currFilter" FilesStatus="@filesStatus" Files2Download="@files2Download"></FilesList>
+
+<DataPager @ref="pagerSMIn2Ev" PageSize="@numRecord" currPage="@currPage" numRecordChanged="@ForceReload" numPageChanged="@ForceReloadPage" totalCount="@totalCount" />
\ No newline at end of file
diff --git a/SMGen/Pages/SMEvent2State.razor.cs b/SMGen/Pages/SMEvent2State.razor.cs
index 34e8a4f..317a661 100644
--- a/SMGen/Pages/SMEvent2State.razor.cs
+++ b/SMGen/Pages/SMEvent2State.razor.cs
@@ -56,6 +56,10 @@ namespace SMGen.Pages
         {
             get => conf.GetValue<bool>("SetupOptions:DoCalcEmptyState");
         }
+        protected string statiCsvPath
+        {
+            get => conf.GetValue<string>("ServerConf:StatiCsvPath");
+        }
 
         protected List<RuleClass> Rules { get; set; } = new List<RuleClass>();
         protected Dictionary<string, int> StatesAll { get; set; } = new Dictionary<string, int>();
@@ -151,10 +155,11 @@ namespace SMGen.Pages
 
                                 case "$DO":
                                     b_rules_definition = false;
-                                    var isOk = checkDirExist(procRootDir);
+                                    var isOk = checkDirExist(Path.Combine(procRootDir, statiCsvPath));
                                     if (isOk)
                                     {
-                                        evaluate_transitions($"{procRootDir}\\{item.Key.Split(".")[0]}.csv", item.Key);
+                                        var fileName = $"{item.Key.Split(".")[0]}.csv";
+                                        evaluate_transitions($"{Path.Combine(procRootDir, statiCsvPath, fileName)}", item.Key);
                                     }
                                     break;
 
@@ -264,7 +269,9 @@ namespace SMGen.Pages
 
                     //await SMGDService.AnagEventinInsert(events2Add);
                     await Task.Delay(1);
-                    //filesStatus[origFileName] = await SMGDService.TranInInsert(TranInList2add, int.Parse(n_state_machine_index));
+                    filesStatus[origFileName] = true;
+
+                    // await SMGDService.TranInInsert(TranInList2add, int.Parse(n_state_machine_index));
 
                     files2Download.Add(origFileName, sz_file2Write);
                 }
diff --git a/SMGen/Pages/SMIn2Event.razor.cs b/SMGen/Pages/SMIn2Event.razor.cs
index 53f64d8..a168c2d 100644
--- a/SMGen/Pages/SMIn2Event.razor.cs
+++ b/SMGen/Pages/SMIn2Event.razor.cs
@@ -52,6 +52,10 @@ namespace SMGen.Pages
         {
             get => conf.GetValue<string>("ServerConf:ProcCsvRootPath");
         }
+        protected string bitCsvPath
+        {
+            get => conf.GetValue<string>("ServerConf:BitCsvPath");
+        }
 
         protected List<RuleClass> Rules { get; set; } = new List<RuleClass>();
         protected List<string> States { get; set; } = new List<string>();
@@ -275,7 +279,8 @@ namespace SMGen.Pages
                                     var isOk = checkDirExist(procRootDir);
                                     if (isOk)
                                     {
-                                        evaluate_transitions($"{procRootDir}\\{item.Key.Split(".")[0]}.csv", item.Key);
+                                        var fileName = $"{item.Key.Split(".")[0]}.csv";
+                                        evaluate_transitions($"{Path.Combine(procRootDir, bitCsvPath, fileName)}", item.Key);
                                     }
                                     break;
 
diff --git a/SMGen/Temp/Rules/PROCESSED/10049_LVF_FANUC.csv b/SMGen/Temp/Rules/PROCESSED/BIT/10049_LVF_FANUC.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/10049_LVF_FANUC.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/10049_LVF_FANUC.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/10063_SEGHETTO_DANOBAT.csv b/SMGen/Temp/Rules/PROCESSED/BIT/10063_SEGHETTO_DANOBAT.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/10063_SEGHETTO_DANOBAT.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/10063_SEGHETTO_DANOBAT.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/10066_FLUITEK_SEMAPHORE.csv b/SMGen/Temp/Rules/PROCESSED/BIT/10066_FLUITEK_SEMAPHORE.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/10066_FLUITEK_SEMAPHORE.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/10066_FLUITEK_SEMAPHORE.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/10067_FLUITEK_FEMCO.csv b/SMGen/Temp/Rules/PROCESSED/BIT/10067_FLUITEK_FEMCO.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/10067_FLUITEK_FEMCO.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/10067_FLUITEK_FEMCO.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/10_Mitsubishi_simple.csv b/SMGen/Temp/Rules/PROCESSED/BIT/10_Mitsubishi_simple.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/10_Mitsubishi_simple.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/10_Mitsubishi_simple.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/11.csv b/SMGen/Temp/Rules/PROCESSED/BIT/11.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/11.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/11.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/15.csv b/SMGen/Temp/Rules/PROCESSED/BIT/15.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/15.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/15.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/17.csv b/SMGen/Temp/Rules/PROCESSED/BIT/17.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/17.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/17.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/18.csv b/SMGen/Temp/Rules/PROCESSED/BIT/18.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/18.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/18.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/19.csv b/SMGen/Temp/Rules/PROCESSED/BIT/19.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/19.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/19.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/1_Simple_Machine.csv b/SMGen/Temp/Rules/PROCESSED/BIT/1_Simple_Machine.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/1_Simple_Machine.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/1_Simple_Machine.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/20_nikkei.csv b/SMGen/Temp/Rules/PROCESSED/BIT/20_nikkei.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/20_nikkei.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/20_nikkei.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/21_DMG1035.csv b/SMGen/Temp/Rules/PROCESSED/BIT/21_DMG1035.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/21_DMG1035.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/21_DMG1035.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/22_COSMAP.csv b/SMGen/Temp/Rules/PROCESSED/BIT/22_COSMAP.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/22_COSMAP.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/22_COSMAP.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/23_EMCO_LM600.csv b/SMGen/Temp/Rules/PROCESSED/BIT/23_EMCO_LM600.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/23_EMCO_LM600.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/23_EMCO_LM600.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/24_EMCO_MM500.csv b/SMGen/Temp/Rules/PROCESSED/BIT/24_EMCO_MM500.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/24_EMCO_MM500.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/24_EMCO_MM500.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/25_ABB_BTB_TECNOTRANSFER.csv b/SMGen/Temp/Rules/PROCESSED/BIT/25_ABB_BTB_TECNOTRANSFER.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/25_ABB_BTB_TECNOTRANSFER.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/25_ABB_BTB_TECNOTRANSFER.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/26_ABB_DOOSAN_main.csv b/SMGen/Temp/Rules/PROCESSED/BIT/26_ABB_DOOSAN_main.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/26_ABB_DOOSAN_main.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/26_ABB_DOOSAN_main.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/27_ABB_DOOSAN_pallet.csv b/SMGen/Temp/Rules/PROCESSED/BIT/27_ABB_DOOSAN_pallet.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/27_ABB_DOOSAN_pallet.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/27_ABB_DOOSAN_pallet.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/28_ABB_RIELLO.csv b/SMGen/Temp/Rules/PROCESSED/BIT/28_ABB_RIELLO.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/28_ABB_RIELLO.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/28_ABB_RIELLO.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/29_EMCO_LM1200.csv b/SMGen/Temp/Rules/PROCESSED/BIT/29_EMCO_LM1200.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/29_EMCO_LM1200.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/29_EMCO_LM1200.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/2_Caber.csv b/SMGen/Temp/Rules/PROCESSED/BIT/2_Caber.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/2_Caber.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/2_Caber.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/30_SCATOLE_INTEC.csv b/SMGen/Temp/Rules/PROCESSED/BIT/30_SCATOLE_INTEC.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/30_SCATOLE_INTEC.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/30_SCATOLE_INTEC.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/46_OSAI_CMS.csv b/SMGen/Temp/Rules/PROCESSED/BIT/46_OSAI_CMS.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/46_OSAI_CMS.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/46_OSAI_CMS.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/54_STD_base_6bit.csv b/SMGen/Temp/Rules/PROCESSED/BIT/54_STD_base_6bit.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/54_STD_base_6bit.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/54_STD_base_6bit.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/5_MoriSeiki_main.csv b/SMGen/Temp/Rules/PROCESSED/BIT/5_MoriSeiki_main.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/5_MoriSeiki_main.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/5_MoriSeiki_main.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/60_STD_MACHINE.csv b/SMGen/Temp/Rules/PROCESSED/BIT/60_STD_MACHINE.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/60_STD_MACHINE.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/60_STD_MACHINE.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/61_STD_DP_MAIN.csv b/SMGen/Temp/Rules/PROCESSED/BIT/61_STD_DP_MAIN.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/61_STD_DP_MAIN.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/61_STD_DP_MAIN.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/62_STD_DP_TAV.csv b/SMGen/Temp/Rules/PROCESSED/BIT/62_STD_DP_TAV.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/62_STD_DP_TAV.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/62_STD_DP_TAV.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/66_FLUITEK_SEMAPHORE.csv b/SMGen/Temp/Rules/PROCESSED/BIT/66_FLUITEK_SEMAPHORE.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/66_FLUITEK_SEMAPHORE.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/66_FLUITEK_SEMAPHORE.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/67_FLUITEK_FEMCO.csv b/SMGen/Temp/Rules/PROCESSED/BIT/67_FLUITEK_FEMCO.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/67_FLUITEK_FEMCO.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/67_FLUITEK_FEMCO.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/6_MoriSeiki_pallet.csv b/SMGen/Temp/Rules/PROCESSED/BIT/6_MoriSeiki_pallet.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/6_MoriSeiki_pallet.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/6_MoriSeiki_pallet.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/7_MoriSeiki_simple.csv b/SMGen/Temp/Rules/PROCESSED/BIT/7_MoriSeiki_simple.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/7_MoriSeiki_simple.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/7_MoriSeiki_simple.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/8_TAV_1_IMP.csv b/SMGen/Temp/Rules/PROCESSED/BIT/8_TAV_1_IMP.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/8_TAV_1_IMP.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/8_TAV_1_IMP.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/9_TAV_2_IMP.csv b/SMGen/Temp/Rules/PROCESSED/BIT/9_TAV_2_IMP.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/9_TAV_2_IMP.csv
rename to SMGen/Temp/Rules/PROCESSED/BIT/9_TAV_2_IMP.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/12_FAMIGLIA_JETCO.csv b/SMGen/Temp/Rules/PROCESSED/STATI/12_FAMIGLIA_JETCO.csv
similarity index 67%
rename from SMGen/Temp/Rules/PROCESSED/12_FAMIGLIA_JETCO.csv
rename to SMGen/Temp/Rules/PROCESSED/STATI/12_FAMIGLIA_JETCO.csv
index 636d412..456f0bf 100644
--- a/SMGen/Temp/Rules/PROCESSED/12_FAMIGLIA_JETCO.csv
+++ b/SMGen/Temp/Rules/PROCESSED/STATI/12_FAMIGLIA_JETCO.csv
@@ -1,5 +1,18 @@
 IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
+12;0;1;13
+12;0;2;2
+12;0;3;3
+12;0;4;33
+12;0;5;5
+12;0;6;34
+12;0;7;7
+12;0;8;8
+12;0;9;9
+12;0;10;10
+12;0;12;11
+12;0;14;11
 12;2;1;13
+12;2;2;2
 12;2;3;3
 12;2;4;33
 12;2;5;5
@@ -12,6 +25,7 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;2;14;11
 12;3;1;13
 12;3;2;2
+12;3;3;3
 12;3;4;33
 12;3;5;5
 12;3;6;34
@@ -25,6 +39,7 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;5;2;2
 12;5;3;3
 12;5;4;33
+12;5;5;5
 12;5;6;34
 12;5;7;7
 12;5;8;8
@@ -38,6 +53,7 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;7;4;33
 12;7;5;5
 12;7;6;34
+12;7;7;7
 12;7;8;8
 12;7;9;9
 12;7;10;10
@@ -50,6 +66,7 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;8;5;5
 12;8;6;34
 12;8;7;7
+12;8;8;8
 12;8;9;9
 12;8;10;10
 12;8;12;11
@@ -62,6 +79,7 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;9;6;34
 12;9;7;7
 12;9;8;8
+12;9;9;9
 12;9;10;10
 12;9;12;11
 12;9;14;11
@@ -74,6 +92,7 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;10;7;7
 12;10;8;8
 12;10;9;9
+12;10;10;10
 12;10;12;11
 12;10;14;11
 12;11;1;13
@@ -86,6 +105,8 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;11;8;8
 12;11;9;9
 12;11;10;10
+12;11;12;11
+12;11;14;11
 12;11;15;12
 12;11;16;13
 12;11;17;14
@@ -102,6 +123,8 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;12;12;11
 12;12;14;11
 12;12;16;13
+12;12;17;12
+12;13;1;13
 12;13;2;2
 12;13;3;3
 12;13;4;33
@@ -114,6 +137,7 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;13;12;11
 12;13;14;11
 12;13;15;12
+12;13;17;13
 12;14;1;13
 12;14;2;2
 12;14;3;3
@@ -142,6 +166,7 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;15;14;11
 12;15;15;12
 12;15;16;13
+12;15;17;15
 12;24;1;13
 12;24;2;2
 12;24;3;3
@@ -156,9 +181,47 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;24;14;11
 12;24;15;12
 12;24;16;13
+12;24;17;24
+12;27;1;13
+12;27;2;2
+12;27;3;3
+12;27;4;33
+12;27;5;5
+12;27;6;34
+12;27;7;7
+12;27;8;8
+12;27;9;9
+12;27;10;10
+12;27;12;11
+12;27;14;11
+12;30;1;13
+12;30;2;2
+12;30;3;3
+12;30;4;33
+12;30;5;5
+12;30;6;34
+12;30;7;7
+12;30;8;8
+12;30;9;9
+12;30;10;10
+12;30;12;11
+12;30;14;11
+12;32;1;13
+12;32;2;2
+12;32;3;3
+12;32;4;33
+12;32;5;5
+12;32;6;34
+12;32;7;7
+12;32;8;8
+12;32;9;9
+12;32;10;10
+12;32;12;11
+12;32;14;11
 12;33;1;13
 12;33;2;2
 12;33;3;3
+12;33;4;33
 12;33;5;5
 12;33;6;34
 12;33;7;7
@@ -172,6 +235,7 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;34;3;3
 12;34;4;33
 12;34;5;5
+12;34;6;34
 12;34;7;7
 12;34;8;8
 12;34;9;9
@@ -180,3 +244,27 @@ IdxFamiglia;IdxStato;IdxTipo;next_IdxStato
 12;34;14;11
 12;34;15;12
 12;34;16;13
+12;35;1;13
+12;35;2;2
+12;35;3;3
+12;35;4;33
+12;35;5;5
+12;35;6;34
+12;35;7;7
+12;35;8;8
+12;35;9;9
+12;35;10;10
+12;35;12;11
+12;35;14;11
+12;50;1;13
+12;50;2;2
+12;50;3;3
+12;50;4;33
+12;50;5;5
+12;50;6;34
+12;50;7;7
+12;50;8;8
+12;50;9;9
+12;50;10;10
+12;50;12;11
+12;50;14;11
diff --git a/SMGen/Temp/Rules/PROCESSED/12_FAMIGLIA_JETCO_CONFRONTO.csv b/SMGen/Temp/Rules/PROCESSED/STATI/12_FAMIGLIA_JETCO_CONFRONTO.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/12_FAMIGLIA_JETCO_CONFRONTO.csv
rename to SMGen/Temp/Rules/PROCESSED/STATI/12_FAMIGLIA_JETCO_CONFRONTO.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/1_BARCODE_MANUALE.csv b/SMGen/Temp/Rules/PROCESSED/STATI/1_BARCODE_MANUALE.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/1_BARCODE_MANUALE.csv
rename to SMGen/Temp/Rules/PROCESSED/STATI/1_BARCODE_MANUALE.csv
diff --git a/SMGen/Temp/Rules/PROCESSED/1_BARCODE_MANUALE_CONFRONTO.csv b/SMGen/Temp/Rules/PROCESSED/STATI/1_BARCODE_MANUALE_CONFRONTO.csv
similarity index 100%
rename from SMGen/Temp/Rules/PROCESSED/1_BARCODE_MANUALE_CONFRONTO.csv
rename to SMGen/Temp/Rules/PROCESSED/STATI/1_BARCODE_MANUALE_CONFRONTO.csv
diff --git a/SMGen/appsettings.json b/SMGen/appsettings.json
index f7ed63a..e5adb27 100644
--- a/SMGen/appsettings.json
+++ b/SMGen/appsettings.json
@@ -11,6 +11,8 @@
   },
   "ServerConf": {
     "ProcCsvRootPath": "Temp\\Rules\\PROCESSED",
+    "BitCsvPath": "BIT",
+    "StatiCsvPath": "STATI",
     "DisableSMGMigrate": true
   },
   "AllowedHosts": "*",